1. Field of the Invention
The present invention relates to improvements in semiconductor memories and, more particularly, to improvements in electrically erasable, electrically programmable read-only memories used for large capacity data storage.
2. Description of the Related Art
The demand for portable and hand held devices which require large amounts of data storage has grown substantially within recent years and is expected to continue to grow well into the next decade. Products such as digital cameras, cellular telephones, personal organizers, voice recording devices and palm top personal computers as well as a host of specialized remote data collection tools are available today and several new products are in development. In nearly all of these products data is stored on solid state electronic media rather than on a hard disk drive, due to the requirements of higher performance, lower energy consumption and superior ruggedness. However, the cost of a given amount of solid state storage media has proven to greatly exceed that of hard disk drive solutions, making it difficult to build attractively priced products which contain enough solid state memory to adequately meet the product requirements.
Recently, a "NAND" type non-volatile memory cell structure has reemerged as a proposed way to reduce manufacturing costs over conventional solid state storage. Higher storage capacity and lower costs are achieved by utilizing a smaller memory cell composed of a single memory transistor which shares each of its nodes with adjacent memory cells. Several such cells are grouped together in a "NAND stack", with their channels in series, along with means to connect the stack ends to a bit line and a reference line. In the past the non-volatile memory transistor used a MNOS non-volatile element, but more recently, floating gate approaches have dominated. In either case the small cell size is the key element which enables higher densities and lower costs.
However, floating gate NAND cells have not been able to realize expected cost reductions due to inherent limitations. Internal write voltages of floating gate NAND memories are typically five to seven times the normal CMOS product power supply limits. Cell sizes are difficult to scale due to the stacked polysilicon floating gate geometry making manufacturing increasingly difficult. Threshold voltages are difficult to control, causing long test times and lower product yields. Each of these factors are intrinsic to the floating gate NAND approach and each significantly affects the product cost.
In the past MNOS (Metal Nitride Oxide Silicon) NAND memory arrays were proposed as a means to realize lower costs. The MNOS structure is conceptually a better approach than the floating gate method, since it is simpler to manufacture, has a naturally tighter threshold voltage distribution, requires minimal test times, and enables much lower write voltages. However, the methods proposed for reading and writing MNOS NAND memories progressively weakens the stored data, destroying it altogether prior to the expected life of the product. This problem is referred to as a "disturb".
Referring now to FIG. 1, current NAND technologies utilize a single transistor floating gate device 10. The drain (D), gate (G), source (S), and bulk (B) contacts, as well as the floating gate (FG) are labeled. Current flows in a channel region between the drain and source when the drain and source are at different potentials, and under direct control of the potential placed on the gate relative to the source and bulk, whose potentials need not be equal. The FG is a non-volatile charge storage node isolated from and between the gate and the channel region. To erase a memory cell, a large negative gate to bulk potential is formed that couples the layer FG to a negative potential, causing holes to be accumulated in the channel region. These holes can tunnel to the FG by the Fowler-Nordheim effect, because of the large electric fields that result from the large gate to bulk potential. Holes on the FG will erase the memory cell to shift the threshold in a negative direction to provide a logic "0" stored state.
To program the memory cell, a large positive gate to bulk potential is formed that couples the FG to a positive potential and inverts the channel region with electrons. As with holes, the electrons can tunnel to the FG by the Fowler-Nordheim effect. The threshold voltage of the memory transistor shifts in the positive direction to provide a logic "1" state.
Conventional NAND technologies are designed such that erased memory cells have depletion thresholds and programmed memory cells have enhancement thresholds. More specifically, the depletion state threshold voltage is achieved when the gate voltage is negative with respect to the source node and the enhancement state threshold voltage is achieved when the gate voltage is positive with respect to the source node. When written, these negative and positive thresholds have a fairly broad distributions, typically in the 1.5-2.0 volt range.
A conventional NAND stack 20 is shown in FIG. 2, where sixteen (16) non-volatile memory cells 10 (MC0-MC15) are placed in series with two n-channel select transistors 11 and 12, transistor 11 being placed at the drain side (MSD) and transistor 12 being placed at the source side (MSS) of the memory transistors 10. Except for memory transistors MC0 and MC15, the drain and source of adjacent memory cells are connected together. The source of memory transistor MC0 is connected to the drain of the next memory cell down, memory transistor MC1. Also, the drain of memory transistor MC0 is connected to the source of memory transistor MSD and the drain of memory transistor MSD is connected to the metal bit line (BL). The drain of memory transistor MC15 is connected to the source of the next memory cell above, memory transistor MC14. Also, the source of memory transistor MC15 is connected to the drain of select transistor MSS and the source of select transistor MSS is connected to the common reference line (CSL), which is typically a diffusion.
It should be noted that the NAND stack unit can be replicated in both the BL direction (column) and orthogonal to the BL direction (row) to form NAND stack arrays of various sizes. NAND stack units in a column connect to a single BL while gates of memory cells within a stack connect to word lines (WL). The gates of the two select transistors connect to select lines (SSL and GSL). The WL's, SSL and GSL run orthogonal to the BLs and are typically formed of polysilicon or a multilayer composite, generally including a silicide on polysilicon. The first memory cells (MC0's) in NAND stack units along the same row are connected to WLO and the last memory cells (MC15's) in NAND stack units along the same row are connected to WL15. This is also true for the other memory cells and the select devices in NAND stack units along the same row.
During reading of the selected memory cell, a current path must be maintained from the selected memory cell to the CSL and BL connections of the NAND stack. Each of the fifteen non-selected NAND cells in the selected NAND stack are rendered conductive by applying sufficient gate to source voltage to not only overcome the positive enhancement threshold voltage but also to provide for a high level of conductance. Then with the gate of the selected memory cell and the CSL of the NAND stack set to ground, the state of the selected cell can be determined by sensing current flow through the selected NAND stack. When the selected memory cell has a negative depletion threshold, current will flow through the NAND stack, and when the selected memory cell has a positive enhancement threshold, little or no current will flow through the NAND stack.
Examples of read, erase and program operation bias schemes are shown in FIG. 3, according to conventional NAND approaches. These biases are applied during a time in which the operation achieves the desired result. A complete wave form diagram would show the conditions before and after these biases as well as the time periods; however, only the change affecting bias conditions are shown here. The read biases are typically active for periods of tens to thousands of nanoseconds and the erase and program biases are active for periods of 100 microseconds to seconds. The amount of time depends on the device size and the performance objectives of the product.
Referring now to FIG. 4, during a read operation, the reference line CSL is at the same potential as the bulk of the NAND transistors, or V.sub.s =ground. The gates of the memory cells in the path of the selected cell and the two select devices are boosted to 4.5 v, and the gate of the selected memory cell is left at the CSL potential. The 4.5 v potential is used, first, to overcome the positive enhancement program thresholds on unselected memory cells, and, second, to achieve suitable conduction. Achieving the second objective depends on the number of unselected devices within the selected NAND stack which are in the positive enhancement program state, which can be anywhere from zero to fifteen. The condition that requires the most gate voltage is that in which the selected memory cell, say MC1, is erased to a negative threshold and all of the unselected memory cells have a high positive threshold and the BL potential is low, say at 1 volt. In this situation, the erased selected memory cell has 0 volts on its gate WL1 and is sinking current from the BL, and the unselected memory cell at the top of the NAND stack (e.g. MC0) has a program threshold. To maintain sufficient conduction through the unselected memory cell, its gate voltage applied to WL0 must be at least V.sub.g =V.sub.tp +V.sub.s +V.sub.on, where V.sub.tp is the enhancement program threshold voltage of MC0, V.sub.s is the source voltage on MC0 and V.sub.on is the additional voltage required to achieve sufficient conductivity.
More specifically, when V.sub.tp is 2.0 volts, V.sub.s is very near the BL voltage of 1.0 volt and V.sub.on should be at least 1.5 volts, so V.sub.g .gtoreq.4.5 volts. A Vg potential of 4.5 volts or higher would require internal boosting above V.sub.cc when the nominal supply voltage V.sub.cc is less than 4.5 volts. This is highly disadvantageous when attempting to optimize device read performance in today's products where V.sub.cc is typically 3.3 volts or below. During a read operation, the time and power required to boost fifteen word lines to 4.5 volts and the two select lines can be substantial. Since the word lines and select lines run completely across the NAND structured memory array, the amount of capacitance that must be boosted to 4.5 volts could be on the order of tens and possibly hundreds of picofarads. Even though this is readily done on today's NAND devices, a method for reading that does not include boosting would be extremely beneficial.
It can be seen that during a read operation, the gate to source potential is greatest on MC15, the memory cell closest to the grounded CSL reference line. If the selected cell is in the conductive erased state, current will flow through the NAND stack; however, there will be little voltage loss between the source of MC15 and the reference line CSL since the selection device MSS is biased well on. Further, if the selected device were in the non-conductive program state, then very little or negligible current would flow through the NAND stack, and the gate to source voltage on MC15 would be nearly exactly equal to the gate voltage on WL15. Thus, the gate to source voltage on MC15 is for all practical purposes equals the voltage on WL15 during read operations.
Furthermore, when reading a NAND device, the address pattern will not necessarily follow a preset sequential pattern, but rather might follow a random or frequently favored partial pattern. Therefore, there is no assurance that each of the rows within a NAND stack will be read in sequence, nor is there assurance that they will ever be read. A worst case analysis would include the condition that only the MC0 is read, and that it is always in the enhancement programmed state. Under this configuration, little or negligible current will flow, and the gate to source voltage on MC1 through MC15 will be nearly equal to their word line voltages. Thus, under worst case conditions, the gate to source voltage on MC1 through MC15 is equal to the worst case gate to source voltage described above for MC15 during typical read operations.
Therefore, when the device is set in a data read mode under worst case conditions, a gate to source bias is applied to transistors MC1 through MC15 within a selected NAND stack. The bias is expected to be V.sub.g .apprxeq.V.sub.tp +V.sub.s +V.sub.on applied during each and every read. As shown in FIG. 3 the gate to source voltage applied to a selected word line during a program mode is of the same polarity as the voltage applied to an unselected word line during a read mode. Even though the program mode voltage is much greater than that used during the read mode, continuous reading during the expected life of the part can cumulatively disturb the stored data much as if it were in the program mode. This disturb problem is manageable if the gate to source voltage is much smaller than that used to program the device. However, this requires that the gate to source voltage be as small as possible or that the program voltage be very large. Neither is desirable and ultimately product performance or reliability must be compromised.
The method employed in NAND devices for programming memory cells is one that programs a single WL at a time. Page buffers are first loaded with data one byte at a time until the desired data is present and then the WL is brought to a high level (V.sub.pp), typically in the 15.5 to 20 volt range. To program a memory cell to a high threshold voltage, 0 volts is transferred to the BL from the data buffer prior to placing Vpp on the selected WL. This creates a high positive gate to channel electric field that causes electrons to tunnel to the FG shifting the threshold voltage positively.
There are two methods primarily used to inhibit the programming of memory cells on the selected word line when using "program inhibit" mode. The first is a method known as "selfboosting". The second is a method using a relatively high inhibit voltage on the bit lines. With the self boosting program inhibit method, unselected WL's are raised to 10 volts and the selected WL is raised to 15 to 20 volts. When these nodes are raised, capacitance between these nodes and the NAND stack channel regions causes the channel potential to rise. Once the NAND stack channel is capacitively coupled above V.sub.cc in the self-boosting method, V.sub.cc is held on the desired BL and on SSL to cut-off the top select device of the NAND stack. Then the channel potential in the NAND stack continues to rise by the capacitive coupling and all the channel regions are coupled to approximately 8 volts to inhibit the programming on the selected WL. In program inhibit method, 8 volts from a latch in the data buffer is placed on the BL associated with the selected WL. This 8 volts is then transferred through the MSD and memory transistors to the channel regions of all memory cells in the NAND stack containing the selected WL which inhibits programming. While programming or program inhibiting, all voltages are above ground.
With either program mode method, the unselected word line voltage is at ten (10) volts. When the selected transistor is to be programmed, zero volts is supplied by the bit line to the channel regions of the transistors within the NAND stack. Even though the program mode voltage is used far less often than the read mode, the voltage is much higher and a minimal amount of program operations can cumulatively disturb the stored data. Ultimately product performance or reliability must be compromised to accommodate this high voltage.
The method used to erase the memory cells in the NAND stack is a bulk method that erases all memory cells connected to the same bulk connection. The gates of all memory cells are held at 0 volts and the bulk is then taken to 21 volts.
As integrated circuit technology advances to smaller geometries and lower operating voltages, it becomes increasingly difficult to accommodate the large voltages required to program and erase conventional devices. Larger than normal geometries and special device structures are required to switch and route the program voltages, ultimately resulting in high final product costs. It is desirable to reduce program voltages in order to improve costs and reliability. Such reduction are limited, however, by the read disturb problem described before. As program voltages are lowered, read voltages become increasingly disturbing.
Therefore, during read and write operations, NAND cell structures require the application of voltage to memory cell gates within the NAND stack to render them conductive and to provide a clear current path to the selected memory cell within the stack. Currently, the applied gate to source voltage on the cells in the path must be of sufficient magnitude to not only overcome an enhancement threshold voltage in the NAND stack cells but also enough to provide sufficient inversion to achieve acceptable current flows. The combined objectives requires a gate to source voltage greater than that which can be reliably used without creating a disturb problem in read and program modes or without requiring internal voltage boosting in read mode.
Therefore, without further innovation the low cost advantages of the NAND approach cannot be used without significantly limiting the number of operations to minimize the effect of disturbs. Further voltages will remain higher than desired and disturb effects will also complicate floating gate product designs.